The technical field of this invention is digital device functional blocks, used generally in the area of microprocessor design and more specifically in the area of digital signal processor devices.
The transfer controller with hub and ports architecture (TCHP), which is the subject of patent application Ser. No. 09/543,970 filed Apr. 6, 2000, now U.S. Pat. No. 6,496,740, is referenced in this text and referred to as simply a centralized transaction processor (CTP). This centralized transaction processor is a significant basic improvement in data transfer techniques in complex digital systems. Along with many other features, the centralized transaction processor allows for uniform implementation of port interfaces at the periphery of such systems. Features of the centralized transaction processor are enhanced when combined with an advanced direct memory access (DMA) processor such as external direct memory access processor external direct memory access of this invention.
The centralized transaction processor functional blocks and their interconnection to the external direct memory access processor are illustrated in the high level diagram of FIG. 1. The centralized transaction processor implementation and feature set are for the most part independent of the external direct memory access functionality. The centralized transaction processor is comprised of hub 100 and ports 111 through 115. It performs the following tasks:
(1) Receives transfer requests in the form of transfer request packets 103 from transfer requester nodes 116 which communicate with the transfer request bus 117; the external direct memory access processor is one of those transfer requesters;
(2) Places these requests in queue manager RAM 102 within the TCHP hub 100;
(3) Prioritizes them by placing them in one of several priority levels within the TCHP hub channel registers 120;
(4) Generates source (read) and destination (write) commands and data for output from the source pipeline 121 and destination pipeline 122;
(5) Broadcasts these source and destination commands and data to all ports 111-115;
(6) Receives read data, acknowledge/status information from ports through the data router 123;
(7) Generates new source (read) and destination (write) commands and data for output from the source pipeline 121 and destination pipeline 122 to the I/O subsystem 123.
The precept behind all direct memory access processors is the same: to perform data movement as a sideband function to normal CPU operation. Depending on the complexity of the DMA, various amounts of central processing unit (CPU) intervention may be required at certain intervals. The goal of any DMA processor is of course for zero CPU intervention, but this is generally not realistic.
While system architectures and requirements vary, the general functions that which a DMA must provide can be categorized into relatively few types. First, a DMA must typically be capable of performing simple linear data movements of one or more data words, where the word size is a function of the CPU or system architecture.
Advanced features of a DMA might include multi-dimensionality, however in general the number of dimensions supported is normally low, about one to three. Indexed addressing is another common feature of an advanced DMA processor, wherein data moves may be performed with a fixed offset between data words. The most advanced DMA processors include support for varying indexes, as might be common for PCI scatter-gather operations.
In addition to support for one or more transfer types, direct memory access has traditionally offered a plurality of channels. A channel generically refers a stored set of parameters, perhaps dynamically updated via the system CPU or DMA itself, which pertain to the movement of one datum source to one datum destination. In general, the number of channels supported linearly maps to the required hardware. This occurs because each channel must monitor and update source, destination, and word counts (and perhaps other parameters) separately for each channel supported.
As one would expect, the number of transfer types supported and the number of channels supported has a large impact on the design complexity with the DMA processor design. Additionally there is the verification cost associated with the design that must be considered.
The external direct memory access processor interfaces with the centralized transaction processor as shown in FIG. 1. The external direct memory access controller submits requests to the centralized transaction processor at one of the transfer request nodes 117 of FIG. 1. The external direct memory access boundary is defined by the heavy dashed line. The centralized transaction processor boundary is defined by the heavy line.
The acronym XDMA was initially derived to describe the function of consolidating multiple external requests, where xe2x80x98Xxe2x80x99 signifies external to the central processing unit (CPU), and xe2x80x98DMAxe2x80x99 refers to the well known direct memory access function. A special category of requesters, mastering peripherals, is of great importance. In a conventional DMA system the peripheral or requester has no control over the actual transaction which is performed. This is instead controlled via the CPU, which sets up the parameters in the DMA control block typically stored in memory mapped registers. The requester is responsible for making the request to the DMA controller.
A classic example of such an operation is a first-in-first-out (FIFO) buffer acting as a requester. The event for such an interface might be the FIFO almost full/empty flag. When set, the DMA engine responds by reading from, or writing to the FIFO, thus servicing it. Note that the FIFO is not capable of setting up the DMA parameters. The CPU must perform that initialization function, as well as any periodic servicing perhaps even resetting the registers after N number of requests have been processed.
The external direct memory access processor of the present invention performs a super-set of the functions of a conventional DMA. The external direct memory access of this invention also provides all the features of the most advanced DMA functions including a full complement of transfer types plus support for a large number of channels. In addition, the external direct memory access architecture is both scalable and flexible without adding significant hardware for increasing the number of channels or modes supported.
This invention includes only generic features of the external direct memory access architecture which are applicable to a wide range of possible designs. In all cases, the external direct memory access interfaces with a centralized transaction processor which ultimately controls all data transfer operations on a microprocessor chip.
Functionally, the external direct memory access processor consists of three main parts. The first part is the event capture and prioritization logic which serves to handle input requests and channel management. The event capture and prioritization logic continuously monitors the incoming requests for N-channels of the external direct memory access. Additionally, it is responsible for responding to these requests by submitting transfer requests to the second portion of the processor, the external direct memory access controller.
External requests might include, but are not limited to, external interrupts routed directly to the external direct memory access processor, on-chip peripherals not serviced in real time by the CPU, and more intelligent mastering peripherals or host CPUs. Mastering peripherals are characterized by their the ability to actively control transaction processing.
The third portion of the external direct memory access processor is the parameter RAM. The parameter RAM is generically the storage facility for the external direct memory access parameters. Because many complex tasks are supported, a high density RAM is very important to the external direct memory access architecture.
The external direct memory access controller performs a superset of all the functions of a conventional DMA. In addition the architecture of the external direct memory access lends itself to a much more scalable and easily maintainable design. Feature enhancements such as new transfer types, or number of events supported, are far simpler to add to the external direct memory access architecture than to a conventional DMA.